Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology

We examine empirically the performance of multi-level logic minimization tools for a lookup table-based Field-Programmable Gate Array (FPGA) technology. The experiments are conducted by using the university tools misII for combinational logic minimization and mustang for state assignment, and the industrial tools xnfmap for technology mapping and apr for automatic placement and routing. We measure the quality of the multi-level logic minimization tools by the number of routed conngurable logic blocks (CLBs) in the FPGA realization. We report three results: a) there is a linear relationship between the number of literals and the number of routed CLBs, and b) in all 34 MCNC-89 benchmark nite state machines, one-hot state assignment resulted in substantially less CLBs than any other state encoding methods available in mustang, c) we present a delay model to provide routing delay prediction based on fanout, and apply the model to estimate the delays of the FPGA implementation of logic expressions prior to technology mapping, place and route. These results are useful for prototyping a design in FPGAs, and then transferring the design to a diierent technology (e.g., CMOS standard cell). It provides valuable information on the diierence in performance of a design realized in diierent technologies.